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Xilinx / mlir-aie

An MLIR-based toolchain for AMD AI Engine-enabled devices.
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How many PLIOs are available from PL to AIE for VCK190 board ? #1902

Open Albresky opened 5 hours ago

Albresky commented 5 hours ago

What's the PLIO channels/lanes available at 128-bit for VCK190 board in PL side ? Accourding to UG1079, the PLIOs support 8 connections from PL side to AIEs with 64-bit data width, given that VCK190 has 39 PLIOs, the total connections/channels/lanes at 128-bit from PL to AIEs should be $39 \times (64/128 \times 8)=156$. However, it was weird that on Vitis2023.2 and later, aiecompiler says "ERROR: [AIE-PRE-MAPPER-11] area group ((0, 0), (49, 0)) has capacity 78 PLIO 128 bit incoming registered channels". But on Vitis 2021.1, aiecompiler DOES SUPPORT 78 PLIOs and more. Is this a software bug?

FYI, I drafted a discussion on Xilinx Community for details of this issue(including testcases).

Albresky commented 5 hours ago

The issue is raised in this repo because maybe this problem is hardware related, and perhaps MLIR-AIE toolchain could give an answer.