Timing closure problem with Alveo U200 and 2 interfaces

[alacamester]

Hi!

I generated the project with command: vivado -mode tcl -source build.tcl -tclargs -board_repo G:/Xilinx/Vivado/2020.2/data/boards/board_files -board au200 -num_phys_func 2 -num_cmac_port 2 (i added the "num_phys_func" argument bcause the included user plugin-box needed it)

The project builds with Vivado 2020.2, but with timing closure errors on the PCIe clock:

Project builds with 1 interface without problem.

L.

[cneely-amd]

Hi @alacamester,

Have you already tried increasing the Vivado Place and Route effort, e.g. by selecting under Tools->Settings->Implementation->Implementation Strategy a more aggressive strategy like Performance Explore? (Also, that failing path in your screenshot is only off by a tiny amount, and I'd expect that generated implementation to probably still run okay on the board.)

Best regards, --Chris

[cneely-amd]

[alacamester]

Thanks for your answer, I'll try that.

Another "future proof" solutions that I can think of:

1. changing placement constraints (to bring PCIe logic closer to the PCIe hard component)
2. ease timing by logic relaxation, extra registers etc. (like in the old ISE days ;) )

What do you think about that? If I have more time I can look into it.

Thanks, L.

[alacamester]

Changing the implementation effort level solved the issue for now. (but this could be a problem later, when someone adds extra logic...)