The Vivado IP "system management wizard" sets the "enable VP/VN" to true by default. This exposes these 2 ports on the IP which are supposed to be connected to pins on the FPGA. But these signals are not broken out in the wrapper nor to the top level. The problem comes in where the IP automatically adds "IOSTANDARD Analog" pin constraints to the design which causes a critical warning because these pins do not exist.
See System Management Wizard v1.3 Product Guide (PG185)
"The System Management Wizard writes the required ANALOG IOSTANDARD constraint on VP/VN ports. Setting the Analog Bank Selection for vaux pins (shown in Figure 4-14) writes the pin LOC and IOSTANDARD constraint for vaux ports."
It makes sense that if these signals are not being routed to the top level that they not be configured in the first place.
The Vivado IP "system management wizard" sets the "enable VP/VN" to true by default. This exposes these 2 ports on the IP which are supposed to be connected to pins on the FPGA. But these signals are not broken out in the wrapper nor to the top level. The problem comes in where the IP automatically adds "IOSTANDARD Analog" pin constraints to the design which causes a critical warning because these pins do not exist.
See System Management Wizard v1.3 Product Guide (PG185)
"The System Management Wizard writes the required ANALOG IOSTANDARD constraint on VP/VN ports. Setting the Analog Bank Selection for vaux pins (shown in Figure 4-14) writes the pin LOC and IOSTANDARD constraint for vaux ports."
It makes sense that if these signals are not being routed to the top level that they not be configured in the first place.
-Wes