Closed tangjie77wd closed 6 years ago
Oh,there is a same situation at https://forums.xilinx.com/t5/Vivado-High-Level-Synthesis-HLS/E-Simulation-failed-SIGSEGV/td-p/805417 ! I think i can solve it by myself according to the solution from the website.
This is a new issue. Here is my code: XiangAnWO3.h file:
`
ifndef _XIANGANWO3H
define _XIANGANWO3H
//#include "hls_video.h" //#include "hls_opencv.h"
include
include "hls_stream.h"
include "opencv2/opencv.hpp"
include "opencv2/imgproc/imgproc.hpp"
include "opencv2/highgui/highgui.hpp"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/common/xf_sw_utils.h"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/common/xf_axi.h"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/common/xf_infra.h"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/imgproc/xf_dilation.hpp"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/imgproc/xf_erosion.hpp"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/imgproc/xf_sobel.hpp"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/imgproc/xf_threshold.hpp"
include "/home/jumper/FPGA_projects/HLS2018.2/xiangAn_wd/xfOpenCV/include/core/xf_magnitude.hpp"
typedef ap_uint<1> uint1; typedef ap_uint<11> uint11;
// maximum image size
define MAX_WIDTH 1936
define MAX_HEIGHT 1456
typedef xf::Scalar<3, unsigned char> RGB_PIXEL; typedef xf::Scalar<1, unsigned char> GRAY_PIXEL;
define NPC1 XF_NPPC1
typedef xf::Mat<XF_8UC3, MAX_HEIGHT, MAX_WIDTH, NPC1> RGB_IMAGE; typedef xf::Mat<XF_8UC1, MAX_HEIGHT, MAX_WIDTH, NPC1> GRAY_IMAGE;
// top level function for HW synthesis uint1 hls_XiangAnWO3(RGB_IMAGE& src_axi,RGB_IMAGE& src_axi2,cv::Mat& src_axi3,RGB_IMAGE& dst_axi, uint11 rows, uint11 cols,uint1 model[16777216]);
endif
`
XiangAnWO3.cpp file: `
include "XiangAnWO3.h"
void FluoDetect(RGB_IMAGE& srcImage,GRAY_IMAGE& FluoImage,uint1 model[16777216]) { GRAY_IMAGE img1(MAX_HEIGHT, MAX_WIDTH); GRAY_IMAGE img2(MAX_HEIGHT, MAX_WIDTH);
pragma HLS DATAFLOW
pragma HLS STREAM variable=img depth=1 dim=1
pragma HLS STREAM variable=img1 depth=1 dim=1
pragma HLS STREAM variable=img2 depth=1 dim=1
pragma HLS loop_flatten off
pragma HLS pipeline II=1
}
void FindTarget(cv::Mat& srcImage,GRAY_IMAGE& dstImage) {
pragma HLS DATAFLOW
pragma HLS INTERFACE register port=srcImage
pragma HLS INTERFACE register port=dstImage
pragma HLS STREAM variable=img1_1 depth=1 dim=1
pragma HLS STREAM variable=img2 depth=1 dim=1
pragma HLS STREAM variable=img3 depth=1 dim=1
pragma HLS STREAM variable=img4 depth=1 dim=1
pragma HLS STREAM variable=img5 depth=1 dim=1
pragma HLS STREAM variable=img1 dim=1
}
void Composition(GRAY_IMAGE& srcImage1,GRAY_IMAGE& srcImage2,RGB_IMAGE& srcImage3,RGB_IMAGE& dstImage) { loop_height: for (int i = 0; i < MAX_HEIGHT; i++) { loop_width: for (int j = 0; j < MAX_WIDTH; j++) {
pragma HLS loop_flatten off
pragma HLS pipeline II=1
}
uint1 hls_XiangAnWO3(RGB_IMAGE& src_axi,RGB_IMAGE& src_axi2,cv::Mat& src_axi3,RGB_IMAGE& dst_axi, uint11 rows, uint11 cols,uint1 model[16777216]) {
pragma HLS INTERFACE s_axilite port=cols bundle=axi_lite
pragma HLS INTERFACE s_axilite port=rows bundle=axi_lite
pragma HLS INTERFACE axis register both port=dst_axi
pragma HLS INTERFACE axis register both port=src_axi3
pragma HLS INTERFACE axis register both port=src_axi2
pragma HLS INTERFACE axis register both port=src_axi
pragma HLS INTERFACE s_axilite port=return bundle=axi_lite
pragma HLS STREAM variable=img_5 depth=1 dim=1
pragma HLS STREAM variable=img_2.data depth=1 dim=1
pragma HLS STREAM variable=img_3.data depth=1 dim=1
} `
Testbeach file: `
include "XiangAnWO3.h"
using namespace std; using namespace cv;
int main (int argc, char* argv) { uint1 rgbarray=new uint1[16777216]; FILE fp_r=NULL; fp_r = fopen("model_mg" , "rb"); if(fp_r!=NULL){ fread(rgbarray, sizeof(uint1), 256256*256, fp_r); fclose(fp_r); }
} `
And the _csim.log file:
INFO: [SIM 2] *************** CSIM start *************** INFO: [SIM 4] CSIM will launch GCC as the compiler. Compiling ../../../src/test.cpp in debug mode Compiling ../../../src/XiangAnWO3.cpp in debug mode Generating csim.exe ERR: [SIM 100] CSim failed with errors. INFO: [SIM 3] *************** CSIM finish ***************
I can not get any useful information from the log file !