Closed liubenyuan closed 1 year ago
Hi, I read the notebook and XRT examples, do I need to manually build the ARP table via the AXI4 Lite interface before the first UDP transaction?
For example the ping_fpga.cpp
demo in XRT writes: https://github.com/Xilinx/xup_vitis_network_example/blob/47063d88843254f3c4c587a85378c51d4bb14696/xrt_host_api/examples/ping_fpga/ping_fpga.cpp#L238
networklayer.arp_discovery();
std::this_thread::sleep_for(std::chrono::seconds(5));
auto table = networklayer.read_arp_table(255);
Thanks again for this great project!
Hi, I finally get VNx works on ADM-PCIE-9V3, use the settings post in this issue #114 The solution is disabling the RS FEC. (Issue #114 can not be commented). The last paragraph in Ethernet folder says that RS FEC should be enabled manually via the AXI4Lite interface.
There is one problem. After writing the bitstream to FPGA and wait for link on, we do UDP test. But everytime, the first UDP transaction will not complete. It stucks at
sock.recv
. The solution is treaky. We burn the bitstream, and do a ping, for example,ping remote_ip
. After that, the first transaction of UDP succeed.Is it the normal behavior of VNx or 100G-fpga-network-core? How could I debug and solve this issue? I guess it must be that the ARP table are not established during first transaction of UDP, so it needs a ping to build the ARP table.
The following is the test code written in python.