Cannot generate PNR for tangnano4k

[Chandler-Kluser]

Hello Everyone,

Firstly, I would like to congratulate the devs for the hard work done to reverse engineer gowin chips architectures to make a free EDA tool.

Secondly, I took the blinky.v project to generate pnr file with yosys and nextpnr-gowin with the following files:

blinky.v:

module top (
    input clk,
    output [`LEDS_NR-1:0] led
);
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk)
    ctr_q <= ctr_d;
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led = ctr_q[25:25-(`LEDS_NR - 1)];
endmodule

tangnano4k.cst:

// these are the HDMI pins!
IO_LOC "led[0]" 27;
IO_LOC "led[1]" 28;
IO_LOC "led[2]" 29;
IO_LOC "led[3]" 30;
IO_LOC "led[4]" 31;
IO_LOC "led[5]" 32;
IO_LOC "key" 15;
IO_LOC "rst" 14;
IO_LOC "clk" 45;
CLOCK_LOC "led[0]" BUFS;
CLOCK_LOC "led[1]" BUFS;
CLOCK_LOC "led[2]" BUFS;
CLOCK_LOC "led[3]" BUFS;
CLOCK_LOC "led[4]" BUFS;
CLOCK_LOC "led[5]" BUFS;
// true LVDS pins
IO_LOC "tlvds_p" 35,34;

and, as I said before, then I used yosys and nextpnr-gowin to generate output.json file to future pack it in an .fs file with the following bash commands:

yosys -D LEDS_NR=6 -D OSC_TYPE_OSCZ -p "read_verilog blinky.v; synth_gowin; write_json blinky.json"
nextpnr-gowin --json blinky.json \
              --write pnrblinky.json \
              --device GW1NSR-LV4CQN48PC7/I6 \
              --cst tangnano4k.cst

Then I have got the following error:

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)

-- Running command `read -define LEDS_NR=6 OSC_TYPE_OSCZ' --

-- Running command `read_verilog blinky.v; synth_gowin; write_json blinky.json' --

1. Executing Verilog-2005 frontend: blinky.v
Parsing Verilog input from `blinky.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing SYNTH_GOWIN pass.

2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\SDP'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Finding top of design hierarchy..
root of   0 design levels: top                 
Automatically selected top as design top module.

2.2.2. Analyzing design hierarchy..
Top module:  \top

2.2.3. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3.3. Executing PROC_INIT pass (extract init attributes).

2.3.4. Executing PROC_ARST pass (detect async resets in processes).

2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$blinky.v:10$1'.
     1/1: $0\ctr_q[25:0]

2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\ctr_q' using process `\top.$proc$blinky.v:10$1'.
  created $dff cell `$procdff$3' with positive edge clock.

2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$blinky.v:10$1'.
Cleaned up 0 empty switches.

2.4. Executing FLATTEN pass (flatten design).
No more expansions possible.

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).

2.7. Executing SYNTH pass.

2.7.1. Executing PROC pass (convert processes to netlists).

2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.7.1.3. Executing PROC_INIT pass (extract init attributes).

2.7.1.4. Executing PROC_ARST pass (detect async resets in processes).

2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).

2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).

2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.7.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

2.7.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.

2.7.5. Executing OPT pass (performing simple optimizations).

2.7.5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.7.5.9. Finished OPT passes. (There is nothing left to do.)

2.7.6. Executing WREDUCE pass (reducing word size of cells).

2.7.7. Executing PEEPOPT pass (run peephole optimizers).

2.7.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.9. Executing TECHMAP pass (map to technology primitives).

2.7.9.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.7.9.2. Continuing TECHMAP pass.
No more expansions possible.

2.7.10. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $add$blinky.v:14$2 ($add).
  creating $alu model for $macc $add$blinky.v:14$2.
  creating $alu cell for $add$blinky.v:14$2: $auto$alumacc.cc:474:replace_alu$4
  created 1 $alu and 0 $macc cells.

2.7.11. Executing SHARE pass (SAT-based resource sharing).

2.7.12. Executing OPT pass (performing simple optimizations).

2.7.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.7.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.7.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.7.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.7.12.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.7.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.7.12.9. Finished OPT passes. (There is nothing left to do.)

2.7.13. Executing FSM pass (extract and optimize FSM).

2.7.13.1. Executing FSM_DETECT pass (finding FSMs in design).

2.7.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.7.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.7.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.7.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.7.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.7.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.7.14. Executing OPT pass (performing simple optimizations).

2.7.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.7.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.7.14.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.7.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.14.5. Finished fast OPT passes.

2.7.15. Executing MEMORY pass.

2.7.15.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

2.7.15.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.15.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.7.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.7.15.5. Executing MEMORY_COLLECT pass (generating $mem cells).

2.7.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).

2.9. Executing TECHMAP pass (map to technology primitives).

2.9.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/brams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GW1NR_SDP'.
Successfully finished Verilog frontend.

2.9.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT1'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\LUT3'.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\DFF'.
Generating RTLIL representation for module `\DFFN'.
Generating RTLIL representation for module `\DFFR'.
Generating RTLIL representation for module `\VCC'.
Generating RTLIL representation for module `\GND'.
Generating RTLIL representation for module `\IBUF'.
Generating RTLIL representation for module `\OBUF'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\ALU'.
Generating RTLIL representation for module `\RAM16S4'.
Generating RTLIL representation for module `\SDP'.
Successfully finished Verilog frontend.

2.9.3. Continuing TECHMAP pass.
No more expansions possible.

2.10. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).

2.11. Executing TECHMAP pass (map to technology primitives).

2.11.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/drams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/drams_map.v' to AST representation.
Generating RTLIL representation for module `\$__GW1NR_RAM16S4'.
Successfully finished Verilog frontend.

2.11.2. Continuing TECHMAP pass.
No more expansions possible.

2.12. Executing DETERMINE_INIT pass (determine init value for cells).

2.13. Updated 0 cells with determined init value.

2.14. Executing OPT pass (performing simple optimizations).

2.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.14.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.14.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.14.5. Finished fast OPT passes.

2.15. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

2.16. Executing OPT pass (performing simple optimizations).

2.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.16.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.16.9. Finished OPT passes. (There is nothing left to do.)

2.17. Executing TECHMAP pass (map to technology primitives).

2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.17.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/arith_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_gw1n_alu'.
Successfully finished Verilog frontend.

2.17.3. Continuing TECHMAP pass.
Using template $paramod\_80_gw1n_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~21 debug messages>

2.18. Executing TECHMAP pass (map to technology primitives).

2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.18.2. Continuing TECHMAP pass.
No more expansions possible.

2.19. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).

2.20. Executing dff2dffs pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into DFFs in top.

2.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 26 unused cells and 14 unused wires.
<suppressed ~27 debug messages>

2.22. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
  $__DFFS_PP1_ -> $__DFFSE_PP1
  $__DFFS_PP0_ -> $__DFFSE_PP0
  $__DFFS_PN1_ -> $__DFFSE_PN1
  $__DFFS_PN0_ -> $__DFFSE_PN0
  $__DFFS_NP1_ -> $__DFFSE_NP1
  $__DFFS_NP0_ -> $__DFFSE_NP0
  $__DFFS_NN1_ -> $__DFFSE_NN1
  $__DFFS_NN0_ -> $__DFFSE_NN0
  $_DFF_PP1_ -> $__DFFE_PP1
  $_DFF_PP0_ -> $__DFFE_PP0
  $_DFF_PN1_ -> $__DFFE_PN1
  $_DFF_PN0_ -> $__DFFE_PN0
  $_DFF_NP1_ -> $__DFFE_NP1
  $_DFF_NP0_ -> $__DFFE_NP0
  $_DFF_NN1_ -> $__DFFE_NN1
  $_DFF_NN0_ -> $__DFFE_NN0
  $_DFF_N_ -> $_DFFE_NP_
  $_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top:

2.23. Executing TECHMAP pass (map to technology primitives).

2.23.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.23.2. Continuing TECHMAP pass.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~26 debug messages>

2.24. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~26 debug messages>

2.25. Executing SIMPLEMAP pass (map simple cells to gate primitives).

2.26. Executing ABC pass (technology mapping using ABC).

2.26.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 26 gates and 52 wires to a netlist network with 26 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
Removed 0 unused cells and 80 unused wires.

2.27. Executing TECHMAP pass (map to technology primitives).

2.27.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/gowin/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/gowin/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.27.2. Continuing TECHMAP pass.
No more expansions possible.

2.28. Executing HILOMAP pass (mapping to constant drivers).

2.29. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
Mapping port top.clk using IBUF.
Mapping port top.led using OBUF.

2.30. Executing DFFINIT pass (set INIT param on FF cells).
Setting top.$auto$simplemap.cc:420:simplemap_dff$100.INIT (port=Q, net=\ctr_q [19]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$101.INIT (port=Q, net=\ctr_q [20]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$102.INIT (port=Q, net=\ctr_q [21]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$103.INIT (port=Q, net=\ctr_q [22]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$104.INIT (port=Q, net=\ctr_q [23]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$105.INIT (port=Q, net=\ctr_q [24]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$106.INIT (port=Q, net=\ctr_q [25]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$81.INIT (port=Q, net=\ctr_q [0]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$82.INIT (port=Q, net=\ctr_q [1]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$83.INIT (port=Q, net=\ctr_q [2]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$84.INIT (port=Q, net=\ctr_q [3]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$85.INIT (port=Q, net=\ctr_q [4]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$86.INIT (port=Q, net=\ctr_q [5]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$87.INIT (port=Q, net=\ctr_q [6]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$88.INIT (port=Q, net=\ctr_q [7]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$89.INIT (port=Q, net=\ctr_q [8]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$90.INIT (port=Q, net=\ctr_q [9]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$91.INIT (port=Q, net=\ctr_q [10]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$92.INIT (port=Q, net=\ctr_q [11]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$93.INIT (port=Q, net=\ctr_q [12]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$94.INIT (port=Q, net=\ctr_q [13]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$95.INIT (port=Q, net=\ctr_q [14]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$96.INIT (port=Q, net=\ctr_q [15]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$97.INIT (port=Q, net=\ctr_q [16]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$98.INIT (port=Q, net=\ctr_q [17]) to 1'0.
Setting top.$auto$simplemap.cc:420:simplemap_dff$99.INIT (port=Q, net=\ctr_q [18]) to 1'0.
Removed 1 unused cells and 2 unused wires.

2.31. Executing HIERARCHY pass (managing design hierarchy).

2.31.1. Analyzing design hierarchy..
Top module:  \top

2.31.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.32. Printing statistics.

=== top ===

   Number of wires:                 60
   Number of wire bits:            165
   Number of public wires:           4
   Number of public wire bits:      59
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                112
     ALU                            26
     DFF                            26
     GND                            52
     IBUF                            1
     OBUF                            6
     VCC                             1

2.33. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.

3. Executing JSON backend.

End of script. Logfile hash: da4e88e879
CPU: user 0.10s system 0.00s, MEM: 17.35 MB total, 11.48 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 32% 13x read_verilog (0 sec), 17% 1x share (0 sec), ...
WARNING: CPU random generator seem to be failing, disabling hardware random number generation
WARNING: RDRND generated: 0xffffffff 0xffffffff 0xffffffff 0xffffffff
Info: Series:GW1NS-4 Device:GW1NSR-4C Package:QFN48P Speed:C7/I6
Info: Cell key not found
Info: Cell rst not found
Info: Cell tlvds_p not found

Info: Packing constants..
Info: Packing GSR..
Info: Packing IOs..
Info: Packing diff IOs..
Info: Packing IO logic..
Info: Packing wide LUTs..
Info: Packing LUT5s..
Info: Packing LUT6s..
Info: Packing LUT7s..
Info: Packing LUT8s..
Info: Packing ALUs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Checksum: 0xa86b5e2b

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xa86b5e2b
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$88_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$89_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$90_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$91_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$92_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$93_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$94_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$87_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$95_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$99_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$97_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$98_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$96_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$100_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$102_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$101_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$85_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$104_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$105_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$106_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$81_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$82_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$83_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$84_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$103_DFFLC'
ERROR: net '$PACKER_GND_NET' user port 'I3' missing on cell '$auto$simplemap.cc:420:simplemap_dff$86_DFFLC'
ERROR: INTERNAL CHECK FAILED: please report this error with the design and full log output. Failure details are above this message.
0 warnings, 27 errors

As you can see, I am in trouble with the net definitions, the .cst file from tangnano4k I took from the example folder from this repository, the same as blinky.v file.

Can someone tell me what is wrong to make me generate the correct output.json file in order to pack it in an .fs file to flash my tangnano4k?

nextpnr-gowin version:

$ nextpnr-gowin --version           
WARNING: CPU random generator seem to be failing, disabling hardware random number generation
WARNING: RDRND generated: 0xffffffff 0xffffffff 0xffffffff 0xffffffff
nextpnr-gowin -- Next Generation Place and Route (Version nextpnr-0.3-37-g8d063d38)

yosys version:

$ yosys -V
Yosys 0.9 (git sha1 1979e0b)

Thanks in advance!!

[pepijndevos]

Since this example is built on every git commit, my first guess is that it's a version problem. Please try updating yosys and nextpnr to the latest git revision. If that does not help, download the python package from the latest CI run in the actions tab, and rebuild nextpr with it. If that fixes the problem, we need to do a new pypi release. I'll do one anyway because we just landed some cool features.

[Chandler-Kluser]

The yosys I was using was from Ubuntu apt repository, which I considered a bit out-of-date, so I compiled a new one from source from the last commit:

$ yosys -V
Yosys 0.18+13 (git sha1 e6a5d8414, clang 14.0.0-1ubuntu1 -fPIC -Os)

and maintained nextpnr-gowin build (I built it this week from source too):

$ nextpnr-gowin --version           
WARNING: CPU random generator seem to be failing, disabling hardware random number generation
WARNING: RDRND generated: 0xffffffff 0xffffffff 0xffffffff 0xffffffff
nextpnr-gowin -- Next Generation Place and Route (Version nextpnr-0.3-37-g8d063d38)

I was able to generate input .json file for nextpnr-gowin from the blinky.v example with no problems as before by doing (this time):

yosys -D LEDS_NR=6 -D OSC_TYPE_OSCZ -p "read_verilog blinky.v; synth_gowin -json blinky.json"

then I could not build the output .json file for packing through nextpnr-gowin:

nextpnr-gowin --json blinky.json \
              --write pnrblinky.json \
              --device GW1NSR-LV4CQN48PC7/I6 \
              --cst tangnano4k.cst

I wasn't able to get the pnrblinky.json due to this error message from nextpnr-gowin:

WARNING: CPU random generator seem to be failing, disabling hardware random number generation
WARNING: RDRND generated: 0xffffffff 0xffffffff 0xffffffff 0xffffffff
Info: Series:GW1NS-4 Device:GW1NSR-4C Package:QFN48P Speed:C7/I6
Info: Cell key not found
Info: Cell rst not found
Info: Cell tlvds_p not found

Info: Packing constants..
Info: Packing GSR..
Info: Packing IOs..
Info: Packing diff IOs..
Info: Packing IO logic..
Info: Packing wide LUTs..
Info: Packing LUT5s..
Info: Packing LUT6s..
Info: Packing LUT7s..
Info: Packing LUT8s..
Info: Packing ALUs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Checksum: 0xe938f891

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xe938f891

Info: Device utilisation:
Info:                    VCC:     1/    1   100%
Info:                  SLICE:    54/ 4608     1%
Info:                    IOB:     7/   98     7%
Info:                   ODDR:     0/   98     0%
Info:           GW_MUX2_LUT5:     0/ 2304     0%
Info:           GW_MUX2_LUT6:     0/ 1152     0%
Info:           GW_MUX2_LUT7:     0/  576     0%
Info:           GW_MUX2_LUT8:     0/  560     0%
Info:                    GND:     1/    1   100%
Info:                    GSR:     1/    1   100%
Info:                   OSCZ:     0/    1     0%

Info: Placed 7 cells based on constraints.
ERROR: Unable to place cell '$PACKER_BUFS2', no BELs remaining to implement cell type 'BUFS'
0 warnings, 1 error

@pepijndevos do you have anything in mind which I can do to overturn this problem?

Thanks in advance!!

[yrabbit]

Judging by the absence of BUFS you used old apicula chip bases when compiling nextpnr. These things are responsible for the long wires and were merged with the main branch not too long ago.

[yrabbit]

nextpnr should work in your case,if you do not use the new mechanisms, but you specified CLOCK_LOC "led[0]" BUFS; and this already requires new bases.

A quick (and dirty) solution is to remove these directives from the .CST

[Chandler-Kluser]

I took the .cst from the apicula example repo folder, is there any .cst better for the board?

[Chandler-Kluser]

I have compiled nextpnr-gowin with the latest apycula from pip (as written in apicula README.md file), do you suggest any other apicula specific version?

[yrabbit]

I took the .cst from the apicula example repo folder, is there any .cst better for the board?

A normal .CST from the repo folder will do ;)

https://github.com/YosysHQ/apicula/blob/master/examples/tangnano4k.cst

(Not the one in the catalog for long wires)

[yrabbit]

I have compiled nextpnr-gowin with the latest apycula from pip (as written in apicula README.md file), do you suggest any other apicula specific version?

I am a bad adviser here because I don't know Python infra and I have no information about the state of packages in PIP;)

!!! Not recommended, manual!!! In general you can still use your version installed from pip because nextpnr only needs the BBA and the bases. You can download the bases from the artifacts of the last build and put them in place of the old bases, and then compile nextpnr from source.

-chipdb

https://github.com/YosysHQ/apicula/actions/runs/2514623030#artifacts

But it is better to wait for pepijndevos

[Chandler-Kluser]

I was able to generate the .fs file using the normal .cst suggested by @yrabbit , compiling apicula from source was not necessary!

Is there any manual or documentation to make these .cst files for my projects?

Thanks in advance @pepijndevos and @yrabbit !!

[yrabbit]

Is there any manual or documentation to make these .cst files for my projects?

We can say that we recognize some subset of the Gowin directives. See appendix A.

https://www.gowinsemi.com/en/support/database/?support_search=physical+constraint