GW1N-9x: Add two rows as normal clock ones

YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

MIT License

465 stars 66 forks source link

Closed yrabbit closed 1 year ago

yrabbit commented 1 year ago

These rows are also nothing special, there are working GB and GT pips.

Signed-off-by: YRabbit rabbit@yrabbit.cyou

yrabbit commented 1 year ago

It still doesn't fix attosoc, but step by step the suspicious places are cleaned up. :)