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YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
MIT License
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stage 2. Add GW1NSR-4C PLLs #154

Closed yrabbit closed 1 year ago

yrabbit commented 1 year ago

A new type of PLL is added - PLLVR, which is used in the GW1NS-4 chips. Both PLL instances are packaged and unpacked with support for all attributes, including static and dynamic setting of generated frequency parameters.

Describes the implicit wires leading to the central clock MUX, which allows us to use all 4 PLL outputs using the global clock networks.

Also the meaning of Table 59 and a couple of attributes in it was discovered. Not used yet, the constants added for the future.

Signed-off-by: YRabbit rabbit@yrabbit.cyou

uis246 commented 1 year ago

Thank you

pepijndevos commented 1 year ago

Kinda ran out of weekend to do any testing on this but CI is green, it looks fine and I saw it working so I'll just merge it, and maybe do some tests before the next release.