stage 2. Add PLL support for GW1NR-4 chips

YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

MIT License

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Closed yrabbit closed 1 year ago

yrabbit commented 1 year ago

These are interesting chips, the two PLLs are asymmetrically placed in one half of the chip and also occupy only two cell

uis246 commented 1 year ago

Unstopable rabbit