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YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
MIT License
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stage2. Add PLL support for GW1NS-2 chips #163

Closed yrabbit closed 1 year ago

yrabbit commented 1 year ago

Also a curious design: some ports are moved so far away from the main cell that a search operation was required:)

Signed-off-by: YRabbit rabbit@yrabbit.cyou