It seems like apicula currently doesn't support the hardware DSP capabilities UG287E.pdf of Gowin FPGA chips.
I'm not currently interested in automatic inference of DSP modules based on higher level Verilog code but I'm looking for a way to manually instantiate MULT18X18 blocks etc.
Hi,
It seems like apicula currently doesn't support the hardware DSP capabilities UG287E.pdf of Gowin FPGA chips.
I'm not currently interested in automatic inference of DSP modules based on higher level Verilog code but I'm looking for a way to manually instantiate MULT18X18 blocks etc.
Am I missing anything?
Thanks a lot for your efforts.