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YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
MIT License
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why you guys so powerful #185

Open quantrpeter opened 1 year ago

quantrpeter commented 1 year ago

hi, gowin fpga seems not open source, why you guys so powerful to generate the bitstream file? How can you do that? thanks

yrabbit commented 1 year ago

It's simple: you take an empty file

module top();
endmodule

generate an image with the vendor IDE, this will be your template, then you add one LUT, generate the image and compare it with the template. Change the position of the LUT and see what changed and what didn't. Take a look at the document https://github.com/YosysHQ/apicula/blob/master/clock_experiments.ipynb or the movies:

https://www.youtube.com/watch?v=Vt7FyOXfkZA&list=PLIYslVBAlKZad3tjr5Y4gqBV3QKQ5_tPw

pepijndevos commented 1 year ago

Or my internship report https://github.com/pepijndevos/internshipreport/releases/download/tag-f2973b39f18d72c18a0ede2d765fb1ff8541cdeb/main.pdf