Properly handle external 9C clock pins

YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

MIT License

446 stars 64 forks source link

Properly handle external 9C clock pins #222

Closed yrabbit closed 6 months ago

yrabbit commented 6 months ago

The GW1NR-9C has interesting clock pins on the bottom side - they do not connect directly to the central MUX, but pass through an additional MUX in the corner cell. Let's take this into account.