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YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
MIT License
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PLL unstable on tec0117 #240

Open pepijndevos opened 3 months ago

pepijndevos commented 3 months ago

I wanted to do some DSP stuff with the Digilent Pmod I2S2 plugged into the Trenz tec0117 board, but ran into issues where the PLL ran at a stuttery 2MHz instead of 25MHz.

In my pursuit of playing with the DSP I opted to select a I2S master clock close enough to the 12MHz USB clock to use that directly, and shelved this problem for later.

So far I've not done much of any debugging. It could be the PLL on the Trenz board is just untested, it could be incorrect configuration, it could be a faulty board, who knows.

Code: https://github.com/pepijndevos/ouisician2/commit/2ee62b15c672f94dc48a0cbc2de7ab988249fd7a

Compiled files, since this uses GHDL speaker.zip

yrabbit commented 3 months ago

Master nextpnr-himbaechel received corrections, can you check if the situation has improved now?

https://github.com/YosysHQ/apicula/pull/241