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YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
MIT License
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HCLK Support #258

Closed Seyviour closed 1 month ago

Seyviour commented 3 months ago

Summary

This pull request documents the CLKDIV and CLKDIV2 HCLK bels for the GW1N-9(C) and GW2A-18(C). A follow up pull request will document pinouts for other devices. This PR also provides two examples of HCLK Bel usage (blinky and DVI), along with documentation on the general structure of HCLK.

Examples

  1. blinky-clkdiv: A blinky example that shows CLKDIV configured with different DIV_MODES. make -f Makefile.himbaechel blinky-clkdiv-tangnano9k.fs
  2. DVI: A simple DVI example that 'wipes' a new colour across the screen every few seconds. make -f Makefile.himbaechel dvi-example-tangnano9k.fs`

Named/Renamed Wires

Along with naming new HCLK wires, this PR renames some others. Specifically, the wires previously named HCLK_OUT have been renamed to HCLK_SECTION_IN to be more descriptive of their apparent function. This renaming does not affect the rest of the current HCLK implementation since the HCLK_OUT name still applies to the wires defined to connect out of HCLK.

Documentation

doc/hclk.md provides documentation on the (currently understood) standard structure of HCLK.

Companion nextpnr PR: https://github.com/YosysHQ/nextpnr/pull/1340

pepijndevos commented 2 months ago

At first glance this looks great, but after the move all my electronics are still in boxes so it's hard for me to test. So if @yrabbit has reviewed and tested it, the nextpnr side is in, and CI passes, it's good to go as far as I'm concerned.

Seyviour commented 2 months ago

Thank you @pepijndevos. There's a bug on the nextpnr side that I need to address first.

pepijndevos commented 1 month ago

Thank you very much!

Seyviour commented 1 month ago

My pleasure. Thanks for merging!