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YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
MIT License
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HCLK. Primary clock pins #263

Closed yrabbit closed 3 months ago

yrabbit commented 4 months ago

We add the ability to use a direct connection of the clock pins on the chip side with the HCLKs input on the corresponding side for the GW1N-9C.

For other chips this standard feature is automatically supported, but 9C is unique - here the wires are renamed.

This is not supported on the bottom side of the chip yet and probably won't be in the near future - but this is not a problem since the external clock generator on the Tangnano9k board is connected to the right side of the chip.

pepijndevos commented 3 months ago

How does this relate to #258 ?

yrabbit commented 3 months ago

This adds another signal source for the HCLK input MUX and therefore for the primitives that lie behind it, including the CLKDIV2/CLKDIV primitives introduced in the above PR 258.