yrabbit
commented
1 month ago I have a few comments on the commands you use:
- You indicate nextpnr to write to the output file with the name pnrled.json, but gowin_pack you start with led.json;
- Tangprimer20k does not belong to the GW2A-18C family, which you indicate for gowin_pack- it belongs to the GW2A-18 family;
- nextpnr-gowin is somewhat outdated and may contain errors that have long been fixed in nextpnr-himbaechel.
#!/bin/sh
yosys -p "read_verilog led.v; synth_gowin -json led.json"
nextpnr-himbaechel --json led.json --write led.json --top led --device GW2A-LV18PG256C8/I7 --vopt family=GW2A-18 --vopt cst=led.cst
gowin_pack -d GW2A-18 -o led.fs led.json
openFPGALoader -b tangprimer20k led.fshttps://github.com/user-attachments/assets/03d3f448-8f7e-43a1-a247-5f887d4ca6e0
Mai-Lapyst
pepijndevos
When using a design that involves the clock of the tangprimer20k, the bitcode created does not properly work on the bord itself. When using the gowin toolchain (IDE or via
gw_sh), it runs fine.The code used is the blinking led example directly from the sipeed website: https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/examples/led.html#New-file
Commands used:
Versions used:
Yosys 0.43 (git sha1 ead4718e5, g++ 14.1.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -ffile-prefix-map=/build/yosys/src=/usr/src/debug/yosys -fPIC -Os)(via arch package: https://archlinux.org/packages/extra/x86_64/yosys/)"nextpnr-gowin" -- Next Generation Place and Route (Version nextpnr-0.7-56-ge9e7dce2)(from AUR: https://aur.archlinux.org/packages/nextpnr-git)Bord: dock-ext v3713, core module v3961
`led.v`:
``` module led( input Clock, output IO_voltage ); /********** Counter **********/ //parameter Clock_frequency = 27_000_000; // Crystal oscillator frequency is 27Mhz parameter count_value = 13_499_999; // The number of times needed to time 0.5S reg [23:0] count_value_reg ; // counter_value reg count_value_flag; // IO change flag always @(posedge Clock) begin if ( count_value_reg <= count_value ) begin //not count to 0.5S count_value_reg <= count_value_reg + 1'b1; // Continue counting count_value_flag <= 1'b0 ; // No flip flag end else begin //Count to 0.5S count_value_reg <= 23'b0; // Clear counter,prepare for next time counting. count_value_flag <= 1'b1 ; // Flip flag end end /********** IO voltage flip **********/ reg IO_voltage_reg = 1'b0; // Initial state always @(posedge Clock) begin if ( count_value_flag ) // Flip flag IO_voltage_reg <= ~IO_voltage_reg; // IO voltage flip else // No flip flag IO_voltage_reg <= IO_voltage_reg; // IO voltage constant end /***** Add an extra line of code *****/ assign IO_voltage = IO_voltage_reg; endmodule ```Constaints `led.cst` (or `fpga_project.cst` in the offical gowin IDE):
``` IO_LOC "IO_voltage" L14; IO_PORT "IO_voltage" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_LOC "Clock" H11; IO_PORT "Clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8; ```