YosysHQ / arachne-pnr

Place and route tool for FPGAs
MIT License
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Obscure error message and core dump when PLL instance can't be routed #100

Closed tomverbeure closed 6 years ago

tomverbeure commented 6 years ago

arachne-pnr -d 8k -P tq144:4k -p blackice-ii.pcf chip.blif -V post_place.v -o chip.txt

The error message:

terminate called after throwing an instance of 'std::out_of_range'
  what():  map::at
Aborted (core dumped)

The design mistake is that the input clock of a SB_PLL40_2F_PAD PLL is also used to clock a FF directly. Arachne should flag this as illegal.

Example attached.

issue.zip

daveshah1 commented 6 years ago

Thanks for reporting this. At some point it would be nice to produce better error messages for all placement and routing failures.

ducky64 commented 6 years ago

The same error appears when instantiating a SB_IO_OD (running the RGB pins as a open-drain GPIO).

The code compiles fine in iCEcube, so I'm not sure what's going on here. While arachne allows signals to be directly connected to the RGB pins, iCEcube requires that they be connected to a SB_IO_OD - so it would appear impossible to get the same code to compile through both toolchains.

Here's the code:

module Top(
  output  foo,
);
  SB_IO_OD #(.PIN_TYPE(25), .NEG_TRIGGER(0)) SB_IO_OD (
    .PACKAGEPIN(foo),
    .DOUT0(1)
  );
endmodule

and the relevant line in the pcf file:

set_io foo 39

(to be fair, a not-that-old version of arachne used to give a fatal error: unknown model `SB_IO_OD', so support for this seems to be somewhat fresh)

tomverbeure commented 6 years ago

@ducky64, I think your case is different than what I reported in that my case was a broken error warning, but the input design was indeed wrong.

In your case, the design seems to be correct yet it’s still bombing. That’s worse.

I suggest that you file a separate issue for this, so that it may get more attention (which it deserves.)

Tom

tomverbeure commented 6 years ago

This issue is a dup of issue #77 and can be closed.