YosysHQ / arachne-pnr

Place and route tool for FPGAs
MIT License
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void Model::check(const Design*) const: Assertion `!p2->is_bidir()' failed #113

Closed whitequark closed 6 years ago

whitequark commented 6 years ago

Non-reduced repro: glasgow_j2mnk25q.zip. It's caused by the clock signal.

daveshah1 commented 6 years ago

As in #114, it looks like you are trying to use an IO both before and after a SB_GB_IO, which is not legal. Use the D_IN_0 output of the SB_GB_IO for this purpose.

whitequark commented 6 years ago

Yes, I know it's not a legal design, but it shouldn't die with an assertion failure. The bug is about that only, sorry, I wasn't clear.

daveshah1 commented 6 years ago

That's fine, I agree with that. I will keep the bug open then.

daveshah1 commented 6 years ago

I realise this is actually a duplicate of #77.

whitequark commented 6 years ago

Ah, thanks for triaging.