Fatal Error: unknown model when parsing blif file

[adamdai]

I am trying to compile and upload generated verilog code using yosys and arachne-pnr, and running into an error with the blif file. I have included the verilog, blif, and pcf files below. stencil.zip So running the following yosys and arachne-pnr command

yosys -q -p 'synth_ice40 -top main -blif stencil.blif' stencil.v
arachne-pnr -q -d 1k -o stencil.txt -p stencil.pcf stencil.blif

I run into this error

stencil.blif:1138: fatal error: unknown model `$mem'
make: *** [stencil.bin] Error 1

Looking at the verilog, it seems its referring to the module coreir_mem (stencil.v, line 739), but it seems like this module should be able to be compiled/supported by ice40. Is it possible that there is a bug in arachne-pnr that is causing this issue?

@leonardt

[leonardt]

It seems that the $mem refers to an instance of the following verilog module (pulled out of the source for convenience). I did some reading and it seems that yosys supports compiling behavioral verilog to the ice40 BRAMs, but perhaps there's something about this module that is causing the issue.

module coreir_mem #(parameter depth=1, parameter has_init=1, parameter width=1) (
  input clk,
  input [width-1:0] wdata,
  input [$clog2(depth)-1:0] waddr,
  input wen,
  output reg [width-1:0] rdata,
  input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
always @(posedge clk) begin
  if (wen) begin
    data[waddr] <= wdata;
  end
end
assign rdata = data[raddr];

endmodule //coreir_mem

Here is the instantiation from line 1442 of the source verilog

  coreir_mem #(.depth(16),.has_init(0),.width(8)) mem(
    .clk(mem__clk),
    .raddr(mem__raddr),
    .rdata(mem__rdata),
    .waddr(mem__waddr),
    .wdata(mem__wdata),
    .wen(mem__wen)
  );

[daveshah1]

The line

assign rdata = data[raddr];

defines a RAM with an asynchronous read port, which is not supported in the iCE40 hardware. Hence Yosys is unable to map it to the iCE40 primitive (tbh I would have expected it to smash it into DFFs and LUTs).

[leonardt]

Got it, makes sense. So we will work around this by changing our memory to have a synchronous read, thanks!