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YosysHQ / arachne-pnr

Place and route tool for FPGAs
MIT License
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Ignore PLLs that are unavailable in the current package #34

Open cliffordwolf opened 8 years ago

cliffordwolf commented 8 years ago

Some of the iCE40 devices have a PLL disabled in certain chip packages. Current git head of Project IceStorm adds this information to the chipdb file.

1K ChipDB file:

.extra_cell 6 0 PLL
LOCKED cb121 cb81 cm49 swg16tr cm36 qn48 vq100

8K ChipDB file:

.extra_cell 16 33 PLL
LOCKED cm81:4k cm81

In commit 45ea318ea76aacc994e0cde2b0ff264469b75920 I added a quick hack to simply ignore those entries.

Ultimately the PLLs should be made unavailable to the placer if arachne-pnr is called with a chip package that has the PLL marked as locked. But I'm not sure about the best way to add this to arachne-pnr.

daveshah1 commented 6 years ago

Should (finally) be fixed in #91