YosysHQ / arachne-pnr

Place and route tool for FPGAs
MIT License
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Handling of LVDS pin constraint #37

Closed mo101 closed 6 years ago

mo101 commented 8 years ago

A minor thing: if an LVDS pin is specified in the .pcf file as the "wrong" one of its pair, arachne-pnr aborts with

arachne-pnr: src/place.cc:1063: void Placer::place_initial(): Assertion `valid(chipdb->cell_location[c].tile())' failed.

rather than producing an error message or (perhaps preferably) correctly allocating both pins. To demonstrate this, take the example in the issue report "Apparently invalid bitstream for LVDS input" and change the pin assignment in the first line of the constraints file from 34 to 33.

cliffordwolf commented 6 years ago

Fixed by #97.