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YosysHQ / arachne-pnr

Place and route tool for FPGAs
MIT License
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LUT interior expression #48

Closed drom closed 7 years ago

drom commented 7 years ago

Currently the output produced by the tool provides the information about the LUT configuration as the number. example: 

  "type": "ICESTORM_LC",
  "parameters": {
    "LUT_INIT": 27030, <-- ???
    "CARRY_ENABLE": 1
  }

It would be beneficial (to visualization / navigation / extraction ... effort) to elaborate on LUT configuration in logical expression form.

Here is example of such format: http://wavedrom.com/tutorial2.html

cliffordwolf commented 7 years ago

The number is the 16 bit truth table for the LUT (e.g. 27030 (dec) is 0110100110010110 (bin)). Since it is only a 4-input function you could probably easily create a Karnaugh map from the LUT bits to get to a minimal sum-of-products expression from its minterms, or minimal product-of-sums expression from its maxterms.

Alternatively you could create a BDD with the LUT bits on it leaves, reduce the BDD, and then display it as a circuit of multiplexers.

drom commented 7 years ago

@cliffordwolf is the order is little endian? Is the following true?


27030 (dec) -->
0110100110010110 (bin)

 3    2    1    0  line
0110.1001.1001.0110

K-map

        i1    i0
       1  0  1  0

i2 0   0  1  1  0
   1   1  0  0  1
i3 0   1  0  0  1
   1   0  1  1  0

Alternative:

i0  1010101010101010
i1  1100110011001100
i2  1111000011110000
i3  1111111100000000

    0110100110010110 (bin)
cliffordwolf commented 7 years ago

This doesn't make much sense:

    i1    i0
   1  0  1  0

It should rather be something like:

   i0=1       i1=0
i1=1 i1=0  i1=1 i1=0

I.e. the two left columns mean i0 is set, the two right columns mean that i0 is cleared.

And then for i1 there is an alternating pattern of columns.

Similar for i2 and i3 and the rows.

Regarding the bit ordering: see https://github.com/cliffordwolf/yosys/blob/master/techlibs/ice40/cells_sim.v#L121 for a model of the SB_LUT4 cell type. I3 selects if the upper or lower half or the truth table is used, I0 selects if an odd or even entry is used. the LSB of the truth table is selected if all inputs are zero.

drom commented 7 years ago

@cliffordwolf I got it. Verilog prototype is better then a hundred words ;)

cseed commented 7 years ago

Looks like @cliffordwolf answered this so I'm going to close it.

drom commented 7 years ago

Yes @cseed , @cliffordwolf answer works!