Open C-Elegans opened 7 years ago
With a similar but larger design, I have also gotten this error
route...
24506 -> 20635
Assertion failed: (unrouted.empty()), function route, file src/route.cc, line 749.
Adding next lines at line 161 of route.cc show the routing issue.
if (chipdb->tile_nets[t].find(tile_net_name) == chipdb->tile_nets[t].end()) { fatal(fmt("failed to rote: " << p->name() << " to " << tile_net_name)); }
Thing is that lutff_7/lout does not exist in chipdb (it only exists for lutff_0 till lutff_6), and guess it that is how it is on real hardware as well, but would be good if @cliffordwolf can confirm that is valid.
Adding next lines at line 161 of route.cc show the routing issue.
Can you create a PR for this?
Thing is that lutff_7/lout does not exist in chipdb
Yes, this is correct afaik. The lout
output of one lut can only be routed to in_2
of the next lut in the tile. For lutff_7
there is no next lut and therefore no lout
signal. (When the FF is disabled then lout
and out
are the same. Otherwise lout
is the signal before the FF.)
Sure, just made it now.
When trying to route a design using LUT instantiation, I get this error:
Does arachne-pnr not support cascading LUTs via the LO port of ICESTORM_LC? I've tried it with both I0 and I2, and it errors both times.
Test case:
test.v:
test.pcf:
built with: