Open mubes opened 6 years ago
Verilog mcve:
module test (input a, z, output reg x, y);
initial x = 0;
initial y = 0;
wire b;
SB_GB_IO gb (
.PACKAGE_PIN(a),
.GLOBAL_BUFFER_OUTPUT(b)
);
always @(posedge a) x <= z;
always @(posedge b) y <= x;
endmodule
BLIF mcve:
.model test
.inputs a z
.outputs x y
.gate SB_DFF C=b D=x Q=y
.gate SB_DFF C=a D=z Q=x
.gate SB_GB_IO GLOBAL_BUFFER_OUTPUT=b PACKAGE_PIN=a
.end
(Originally posted as yosys issue #427)
I think I got to the bottom of this. When a clock is used for a global buffer using something like;
SB_GB_IO BtraceClk0 ( .PACKAGE_PIN(traceClk), .GLOBAL_BUFFER_OUTPUT(BtraceClk) );
you will got the following error if you try to use traceClk rather than BtraceClk elsewhere in the design;
arachne-pnr: src/netlist.cc:657: void Model::check(const Design*) const: Assertion `!p2->is_bidir()' failed. ./create: line 2: 4153 Aborted (core dumped) arachne-pnr -d 8k -P ct256 -p toplevel.pcf tracIF.blif -o traceIF.txt
Yes, it's probably something only a fool would have tried, but never underestimate the ingenuity of fools....
(I have code in a repository that exhibits this issue, but its otherwise in a horribly broken state so please PM or Gitter me for a link if you need it to re-create the problem usng my codebase ... it will be opensource, just not ready yet).
DAVE