Open matthiasbock opened 5 years ago
The problem is you are using two CORE variant PLLs, which conflicts with the fact that clock_10mhz is at a dedicated PLL input pin. Use one CORE and one 2-output PAD PLL, passing the pass-through second output of the latter into the reference input of the former.
Lattice's website states, that iCE40-HX4k and -HX8k both feature two PLLs.
I created a Verilog project in which I use both PLLs. Synthesis with YoSys completes successfully, however placement of the second PLL fails with both arachne-pnr and nextpnr. In the nextpnr-gui I could not find a second PLL bel, therefore I suspect it might be missing from the chipdb.
Here you can find a simple project reproducing the issue:
(I tried attaching a ZIP to this issue, but for some reason that didn't work.)
Building with arachne-pnr
Building with nextpnr