icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE

YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

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icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE #257

Closed smunaut closed 4 years ago

smunaut commented 4 years ago

This allows selection of the div-by-5 mode of the PLL. This bit can't be fuzzed because it's not supported by the lattice tools at all ...

It's only been tested on the UP5k, the other positions are educated guesses. TBH it might not even exist on older FPGA variants HX/LP ...

Signed-off-by: Sylvain Munaut tnt@246tNt.com

smunaut commented 4 years ago

Updated the PR since after testing, the suspicion that HX/LP might not support that mode was confirmed (at least for HX but I'd expect LP to be the same). So I limited this to the only known working UP5k.