Prevent icepll from generating settings below lower bound

YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

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Prevent icepll from generating settings below lower bound #270

Open olofk opened 3 years ago

olofk commented 3 years ago

Here's an example of when this is a problem https://github.com/olofk/serv/pull/37#issuecomment-702676384

smunaut commented 3 years ago

I don't think that's correct.

1) The absolute output path from the PLL should be fully static AFAICT so as long as the PFD and VCO (which really are the only 2 elements with dynamic behavior) are within range, it should be fine.

2) Also ... 15.938 M is close enough to 16 M that it's not going to fail ...

This requires would require much more testing to get to the bottom of the issue with minimal reproducers and looking directly at the PLLL output with a scope.