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YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
ISC License
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Add an option (-p) to icepll to force use of SB_PLL40_PAD #278

Closed davidthings closed 2 years ago

davidthings commented 3 years ago

When a clock is applied to a dedicated clock pin, SB_PLL40_CORE is no longer the correct primitive to use.

Also the name of the clock input must be PACKAGEPIN (rather than REFERENCECLK)

This switch allows the easy use of icepll with hardware that connects clock signals to dedicated clock signal pins (like the Lattice iCE40 UltraPlus Breakout Board, iCEBreaker, iCEBreaker Bitsy, Fomu etc.)

(Addresses Issue https://github.com/YosysHQ/icestorm/issues/190)

smunaut commented 2 years ago

Small nitpick: The phrasing in the commit is a bit misleading.

It's not if the clock is applied to a dedicated clock pin that the PAD variant must be used. It's if it's applied to the specific clock pin co-located with the PLL instance. (Any other global clock input pin won't do, there is a single one per PLL).