It looks like the NegClk configuration bits on the UP5K for the read and write ports may be swapped.
I can verify the read clock polarity is not affected when a SB_RAM40_4KNR is instantiated, but is altered when a SB_RAM40_4KNW cell is used instead. The timing analysis will be incorrect as well. I have not run any tests to be able to infer the clock polarity of the write port.
I get the expected clock behavior testing with the HX1K, although I stumbled across a different potential issue which I can address separately.
EDIT: Looks like this is actually a nextpnr issue. I'll open a new issue there instead.
It looks like the NegClk configuration bits on the UP5K for the read and write ports may be swapped.
I can verify the read clock polarity is not affected when a SB_RAM40_4KNR is instantiated, but is altered when a SB_RAM40_4KNW cell is used instead. The timing analysis will be incorrect as well. I have not run any tests to be able to infer the clock polarity of the write port.
I get the expected clock behavior testing with the HX1K, although I stumbled across a different potential issue which I can address separately.
EDIT: Looks like this is actually a nextpnr issue. I'll open a new issue there instead.