YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
ISC License
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icepll enhancements #303

Open duskwuff opened 1 year ago

duskwuff commented 1 year ago

1) support PHASE_AND_DELAY + SHIFTREG feedback, which uses a 4x VCO multiplier behind the scenes

2) allow overriding clock constraints, just in case you like to live on the edge. my testing suggests that the 10 MHz F_pfd minimum is highly flexible, for example