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YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
ISC License
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continue 4bc68c9 Fix icebox_vlog for up5k #318

Open majbthrd opened 10 months ago

majbthrd commented 10 months ago

I was confronted with this when attempting to use icebox_vlog with a up5k image:

Traceback (most recent call last):
  File "/home/user/icestorm/icebox/./icebox_vlog.py", line 537, in <module>
    text_func.append("  .SHIFTREG_DIV_MODE(1'b%s)," % get_pll_bit(pllinfo, "SHIFTREG_DIV_MODE"))
  File "/home/user/icestorm/icebox/./icebox_vlog.py", line 186, in get_pll_bit
    bit = pllinfo[name]
KeyError: 'SHIFTREG_DIV_MODE'

The fault looks suspiciously like another fault already fixed by previous PR #263, and so I've applied the same @daveshah1 correction.