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YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
ISC License
963 stars 224 forks source link

icepll: add option for reset input to generated module #321

Open machinaut opened 5 months ago

machinaut commented 5 months ago

This gives me a bit more flexibility to have a build system generate clock modules which can be used directly, without needing to modify them.