Ultra / UltraPlus support

drom commented 7 years ago

As we discussed on the twitter: https://twitter.com/oe1cxw/status/821646243101372417 it would be nice to have support for the latest / greatest FPGAs. Created this ticket to scope the work need to be done:

New features (in priority order?)

DSP blocks. (MULT16 + ACC32) iCE5LP1K = 2; iCE5LP2K/4K = 4; iCE40UP3K = 4; iCE40UP5K = 8;
SPRAM 256 kibit. iCE40UP3K/5K = 4 blocks;
HF (48MHz), LF (10KHz) Oscillator
Other Hard-IPs, I2C, SPI, PWM, etc.

Affected tools

icestorm , new blocks, new devices (resource configuration?)
yosys , resource inference, instantiation?
arachne-pnr , placement, routing information for new resources?

Next steps

make sense to start with the flagman chip on Eval board: http://www.digikey.com/short/3fpvm3
stab unknown parts of the bitstream with predefined sequences, to achieve ic40 functionality
propagate stabs for all tools
work on feature by feature basis

dbetz commented 6 years ago

Thanks! That was it. I removed the -S and the LEDs are mostly working. The red one doesn't seem to ever come on but that's probably because I didn't do a good job of soldering it on the board. For some reason my Upduino board came without the RGB LED soldered in place. The LED was just loose in the package.

mrithyufpga commented 4 years ago

What is the configuration time of SRAM from NVCM for Device is ICE40UP5K-UWG30ITR. It is mentioned, The on-chip NVCM allows the device to configure instantly I want to know the time duration of "instantly" here. referred FPGA-TN-02001-3.2. Can anyone help me on this

daveshah1 commented 4 years ago

icestorm does not support the NVCM currently and I don't know anyone here using it, so you may be better off asking somewhere else.

majbthrd commented 3 years ago

What is the configuration time of SRAM from NVCM for Device is ICE40UP5K-UWG30ITR. It is mentioned, The on-chip NVCM allows the device to configure instantly I want to know the time duration of "instantly" here. referred FPGA-TN-02001-3.2. Can anyone help me on this

@mrithyufpga, this is probably too late for you, but it may help others like myself who arrived here wanting to know the same thing.

As you may know, the claim in Lattice document FPGA-TN-02001 (formerly TN1248) is "The on-chip NVCM allows the device to configure instantly" but nowhere in the datasheet is any specifications of this time.

I was also curious what "instantly" really meant, and I had a spare iCE40 Ultra Breakout Board (iCE5LP4K) to test with.

The answer appears to be: the configuration time is no faster than with an external SPI flash! The person who wrote the "instantly" claim has an unusual interpretation of that word.

I instrumented the DUT with a scope both before and after programming. The time between CRESET being de-asserted and DONE being asserted was 50.71 milliseconds both with "Master SPI" mode (FPGA pulls data from external PROM) and with NVCM programmed (external flash PROM erased for good measure).

In both "Master SPI" and NVCM, the FPGA clocks SPI_SCK from the de-assertion of CRESET until the FPGA is configured (DONE asserted). (That was a major disappointment for me, as I hoped OTP would stop the FPGA from driving SPI signals.)

The changes from "Master SPI" to NVCM mode are that: a) there is no longer traffic on SPI_SO and SPI_SI b) SPI_SS_B is still driven until DONE, but is driven inactive (logic '1')

YosysHQ / icestorm