Error: spawn C:\oss-cad-suite\bin\gowin_pack ENOENT

[tuanhth95]

i follow step by step instructions on youtube video: https://www.youtube.com/watch?v=Y8koTqfXN3M&t=17s i use oss-suite-cad latest 16-02-2024 and i meet the error in the title, below is full output of me, how can i fix it: Starting FPGA Toolchain Starting Yosys CST Checking /----------------------------------------------------------------------------\			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 \----------------------------------------------------------------------------/
Parsing Counter.v
    - Module top parsed
Checking if all ports are defined in constraints file
All Ports are defined

Finished CST Checking Starting Synthesys with Yosys (Gowin) Step 1: Executing Verilog-2005 frontend: c:\Users\tuan\Desktop\Counter_sipeed\Counter.v Step 2: Executing SYNTH_GOWIN pass. Step 2.1: Executing Verilog-2005 frontend: C:\OSS-CA~1\bin../share/yosys/gowin/cells_sim.v Step 2.2: Executing Verilog-2005 frontend: C:\OSS-CA~1\bin../share/yosys/gowin/cells_xtra.v Step 2.3: Executing HIERARCHY pass (managing design hierarchy). Step 2.4: Executing PROC pass (convert processes to netlists). Step 2.5: Executing FLATTEN pass (flatten design). Step 2.6: Executing TRIBUF pass. Step 2.7: Executing DEMINOUT pass (demote inout ports to input or output). Step 2.8: Executing SYNTH pass. Step 2.9: Executing MEMORY_LIBMAP pass (mapping memories to cells). Step 2.10: Executing TECHMAP pass (map to technology primitives). Step 2.11: Executing OPT pass (performing simple optimizations). Step 2.12: Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Step 2.13: Executing OPT pass (performing simple optimizations). Step 2.14: Executing TECHMAP pass (map to technology primitives). Step 2.15: Executing OPT pass (performing simple optimizations). Step 2.16: Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). Step 2.17: Executing OPT_CLEAN pass (remove unused cells and wires). Step 2.18: Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Step 2.19: Executing TECHMAP pass (map to technology primitives). Step 2.20: Executing OPT_EXPR pass (perform const folding). Step 2.21: Executing SIMPLEMAP pass (map simple cells to gate primitives). Step 2.22: Executing Verilog-2005 frontend: C:\OSS-CA~1\bin../share/yosys/abc9_model.v Step 2.23: Executing ABC9 pass. Step 2.24: Executing TECHMAP pass (map to technology primitives). Step 2.25: Executing OPT_LUT_INS pass (discard unused LUT inputs). Step 2.26: Executing SETUNDEF pass (replace undef values with defined constants). Step 2.27: Executing HILOMAP pass (mapping to constant drivers). Step 2.28: Executing AUTONAME pass. Step 2.29: Executing HIERARCHY pass (managing design hierarchy). Step 2.30: Printing statistics. Step 2.31: Executing CHECK pass (checking for obvious problems). Step 2.32: Executing JSON backend.

Summary
    Number of wires:                  77
    Number of wire bits:             121
    Number of public wires:           77
    Number of public wire bits:      121
    Number of memories:                0
    Number of memory bits:             0
    Number of processes:               0
    Number of cells:                  82
        ALU                           30
        DFFE                           6
        DFFR                          24
        GND                            1
        IBUF                           1
        LUT1                           4
        LUT4                           7
        MUX2_LUT5                      2
        OBUF                           6
        VCC                            1

Finished Synthesys Starting PnR with NextPnR Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5 Packing constants.. Packing Shadow RAM.. Packing GSR.. No GSR in the chip base Packing IOs.. Packing diff IOs.. Packing IO logic.. Packing wide LUTs.. Packing LUT5s.. Packing LUT6s.. Packing LUT7s.. Packing LUT8s.. Packing ALUs.. Packing LUT-FFs.. Packing non-LUT FFs.. Packing PLLs.. Checksum: 0x3c6f1c13 Placed 7 cells based on constraints. Creating initial analytic placement for 41 cells, random placement wirelen = 1954. Running main analytical placer, max placement attempts per cell = 10000. HeAP Placer Time: 0.05s Running simulated annealing placer for refinement. SA placement time 0.03s Max frequency for clock 'clk_IBUF_I_O': 316.86 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 3.26 ns Checksum: 0x0bed5c4f Find global nets... Routing globals... Routing.. Setting up routing queue. Routing 219 arcs. Routing complete. Router1 time 2.17s Checksum: 0x5399df7f Max frequency for clock 'clk_IBUF_I_O': 315.86 MHz (PASS at 27.00 MHz) Max delay posedge clk_IBUF_I_O -> : 2.70 ns Program finished normally.

Device Utilisation:
    VCC:               1/    1   100%
    SLICE:            73/ 8640     0%
    IOB:               7/  274     2%
    OSER16:            0/   38     0%
    IDES16:            0/   38     0%
    IOLOGIC:           0/  296     0%
    MUX2_LUT5:         2/ 4320     0%
    MUX2_LUT6:         0/ 2160     0%
    MUX2_LUT7:         0/ 1080     0%
    MUX2_LUT8:         0/ 1056     0%
    GND:               1/    1   100%
    RAMW:              0/  270     0%
    OSC:               0/    1     0%
    rPLL:              0/    2     0%

Finished PnR Starting Bitstream Generation with Apicula Receieved Error Error spawn C:\oss-cad-suite\bin\gowin_pack ENOENT Error: spawn C:\oss-cad-suite\bin\gowin_pack ENOENT at Process.onexit (node:internal/child_process:283:19) at onErrorNT (node:internal/child_process:476:16) at process.processTicksAndRejections (node:internal/process/task_queues:82:21) Finished Bitstream Generation Task finished with errors exiting Toolchain Completed

[mmicko]

Hi. Due to some cross compilation issues there was a big problem packaging windows version of numpy (library used by apicula, gowin_pack) so that needed to be addressed. Since that is no longer dependency, I will just need some time to change build scripts and make sure all is running fine for all supported platforms. Will close this issue when new build supports it.

[mmicko]

Windows build is now update and rebuilt, so you can download latest build and tryout if it works for you