I have been working on a university project developing RISC-V processor designs. Up until recently,
we have been using Xilinx FPGAs but have started to migrate to Lattice FPGAs and the oss-cad-suite.
Since the start of the migration, we have been searching for an RTL schematic viewer similar to
the one included with Vivado. We need a tool that allows us to interact with the schematic by
moving and zooming, highlighting signals to trace them, viewing the schematic of submodules,
using common electrical symbols for the components, and naming the ports, signals, and components.
This functionality helps new students joining the project to understand how the design is created
from smaller components and how they are structured.
During our search, we found two tools that generate RTL diagrams but lack some functionalities.
First, we tried the functionality integrated into Yosys, but the dot files generated are often
hard to understand, especially as designs get bigger. One problem is the way Graphviz routes the
connections: they are not right-angled and sometimes all over the place, making it difficult to
understand the schematic. We found no way to configure this. Additionally, the symbols used make
it harder to understand the diagrams, combined with more complicated logic displayed as blocks
that only denote the lines in the Verilog sources they represent.
The second tool we tried is netlistsvg,
which generates RTL schematics as SVG files directly
from Yosys's general synthesis results. While this tool matches our needs better, with right-angled
connections and common, replaceable symbols, it still has some shortcomings. For example, it does not
name the components, ports, and wires, making it harder to understand the design. It also either shows
the flattened design or only the top level with boxes depicting the submodules.
This has led me to consider developing such a tool. The idea is to use Qt or GTK to create a program
that displays an RTL diagram, similar to netlistsvg, using the JSON representation of the hardware
generated by Yosys. I would add functionality to interactively browse the diagram, manipulate the
view, show labels, and display the schematics of submodules.
Does anyone have pointers to libraries or tools that would help during the development of such a program?
I have already found a library called libavoid,
which does orthogonal routing with avoidance, and it
looks promising for routing the signals around the components of the diagram.
Hello everyone,
I have been working on a university project developing RISC-V processor designs. Up until recently, we have been using Xilinx FPGAs but have started to migrate to Lattice FPGAs and the oss-cad-suite.
Since the start of the migration, we have been searching for an RTL schematic viewer similar to the one included with Vivado. We need a tool that allows us to interact with the schematic by moving and zooming, highlighting signals to trace them, viewing the schematic of submodules, using common electrical symbols for the components, and naming the ports, signals, and components. This functionality helps new students joining the project to understand how the design is created from smaller components and how they are structured.
During our search, we found two tools that generate RTL diagrams but lack some functionalities.
First, we tried the functionality integrated into Yosys, but the dot files generated are often hard to understand, especially as designs get bigger. One problem is the way Graphviz routes the connections: they are not right-angled and sometimes all over the place, making it difficult to understand the schematic. We found no way to configure this. Additionally, the symbols used make it harder to understand the diagrams, combined with more complicated logic displayed as blocks that only denote the lines in the Verilog sources they represent.
The second tool we tried is netlistsvg, which generates RTL schematics as SVG files directly from Yosys's general synthesis results. While this tool matches our needs better, with right-angled connections and common, replaceable symbols, it still has some shortcomings. For example, it does not name the components, ports, and wires, making it harder to understand the design. It also either shows the flattened design or only the top level with boxes depicting the submodules.
This has led me to consider developing such a tool. The idea is to use Qt or GTK to create a program that displays an RTL diagram, similar to netlistsvg, using the JSON representation of the hardware generated by Yosys. I would add functionality to interactively browse the diagram, manipulate the view, show labels, and display the schematics of submodules.
Does anyone have pointers to libraries or tools that would help during the development of such a program? I have already found a library called libavoid, which does orthogonal routing with avoidance, and it looks promising for routing the signals around the components of the diagram.
Thank you for your help and suggestions!