When trying to run it in Verilator, I get 134 warnings, e.g. Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS's SIGNED generates 32 bits.. I can disable all warnings, but then I don't see the warnings in my code, and I try always to write code with no warnings, because I'm a HDL noob and this saves my life. Could you fix all warnings? Attached is the full list.
warnings.txt
When trying to run it in Verilator, I get 134 warnings, e.g.
Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS's SIGNED generates 32 bits.. I can disable all warnings, but then I don't see the warnings in my code, and I try always to write code with no warnings, because I'm a HDL noob and this saves my life. Could you fix all warnings? Attached is the full list. warnings.txt