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PicoRV32 - A Size-Optimized RISC-V CPU
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multiple assignments to same net in always block in instruction decoder #169

Open NAGA241 opened 4 years ago

NAGA241 commented 4 years ago

signals like is_beq_bne_blt_bge_bltu_bgeu, is_lb_lh_lw_lbu_lhu, decoded_imm_j, are assigned values more than once in an always blocl in nested loops. If there is a case which activates compressed_isa then as per the code there are two simultaneous non-blocking assignments to these signals. Does the code work like this ? Please correct me if I am wrong.