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YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU
ISC License
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Add big-endian support #172

Open zeldin opened 4 years ago

zeldin commented 4 years ago

This PR adds an option to picorv32 to build it in big endian mode. The instruction stream format mandated by UCB for big endian systems can be enabled with a separate option. If this option is not enabled, an instruction stream generated for LE can be used (but note that sub-word rodata, such as string literals, will not be correct) in lieu of a big endian tool chain.

Tested on iCE40 HX8K hardware, including compressed instruction streams in the big endian format.

zeldin commented 4 years ago

Note: I have also updated binutils and gcc to support big endian code generation, here and here.

zeldin commented 4 years ago

I updated the code to follow the latest version of the RISC-V specification which calls for fully little-endian instruction encoding on big-endian RISC-V.

Updated toolchains are here: https://github.com/zeldin/riscv-binutils-gdb/commits/big-endian https://github.com/zeldin/riscv-gcc/commits/big-endian