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YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU
ISC License
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make icebsynsim doesn't seem to work, while make hx8ksynsim does #175

Open ghost opened 4 years ago

ghost commented 4 years ago

Following from a clean git checkout today, commands are run in a container with the latest versions of dependencies. In short:

I thought it might be due to using nextpnr-ice40 and json vs arachne-pnr and blif, but I changed that for hx8kdemo, and it still works (see diff + run at the end)

make hx8ksynsim, this works and gives serial output:

root@660aae5e3d01:/workdir/picosoc# make hx8ksynsim
yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -blif hx8kdemo.blif' hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
yosys -p 'read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v'

 Yosys 0.9+3541 (git sha1 04d5692a, clang 6.0.0-1ubuntu2 -fPIC -Os)

-- Running command `read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v' --

1. Executing BLIF frontend.

2. Executing Verilog backend.
Dumping module `\hx8kdemo'.

End of script. Logfile hash: 709401f83e, CPU: user 2.66s system 0.00s, MEM: 35.14 MB peak
Yosys 0.9+3541 (git sha1 04d5692a, clang 6.0.0-1ubuntu2 -fPIC -Os)
Time spent: 94% 2x write_verilog (2 sec), 5% 2x read_blif (0 sec)
iverilog -s testbench -o hx8kdemo_syn_tb.vvp hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v `yosys-config --datdir/ice40/cells_sim.v`
riscv32-unknown-elf-cpp -P -DHX8KDEMO -o hx8kdemo_sections.lds sections.lds
riscv32-unknown-elf-gcc  -DHX8KDEMO -march=rv32imc -Wl,-Bstatic,-T,hx8kdemo_sections.lds,--strip-debug -ffreestanding -nostdlib -o hx8kdemo_fw.elf start.s firmware.c
riscv32-unknown-elf-objcopy -O verilog hx8kdemo_fw.elf hx8kdemo_fw.hex
vvp -N hx8kdemo_syn_tb.vvp +firmware=hx8kdemo_fw.hex
VCD info: dumpfile testbench.vcd opened for output.
00000000
00000001
+50000 cycles
00000011
00000111
00001111
00011111
Serial data: 'B'
Serial data: 'o'
Serial data: 'o'
Serial data: 't'
Serial data: 'i'
Serial data: 'n'
+50000 cycles
Serial data: 'g'
Serial data: '.'
Serial data: '.'
Serial data:  13
Serial data:  10
00111111
+50000 cycles
01111111
11111111
Serial data: 'P'
Serial data: 'r'
+50000 cycles
Serial data: 'e'
Serial data: 's'
Serial data: 's'
Serial data: ' '
Serial data: 'E'
Serial data: 'N'
Serial data: 'T'
Serial data: 'E'
Serial data: 'R'
Serial data: ' '
Serial data: 't'
Serial data: 'o'
Serial data: ' '
Serial data: 'c'
Serial data: 'o'
Serial data: 'n'
Serial data: 't'
Serial data: 'i'
Serial data: 'n'
Serial data: 'u'
Serial data: 'e'
Serial data: '.'
Serial data: '.'
Serial data:  13
Serial data:  10
+50000 cycles

make icebsynsim, this runs, but gives no serial output

c:\Storage\fpga\picorv32>.\_shell.cmd
root@26bdd59bcffe:/workdir/picosoc# make icebsynsim
yosys -ql icebreaker.log -p 'synth_ice40 -top icebreaker -json icebreaker.json' icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v'

 Yosys 0.9+3541 (git sha1 04d5692a, clang 6.0.0-1ubuntu2 -fPIC -Os)

-- Running command `read_json icebreaker.json; write_verilog icebreaker_syn.v' --

1. Executing JSON frontend.
Importing module icebreaker from JSON tree.
Importing module SB_WARMBOOT from JSON tree.
Importing module SB_SPRAM256KA from JSON tree.
Importing module SB_SPI from JSON tree.
Importing module SB_RGB_DRV from JSON tree.
Importing module SB_RGBA_DRV from JSON tree.
Importing module SB_RAM40_4KNW from JSON tree.
Importing module SB_RAM40_4KNRNW from JSON tree.
Importing module SB_RAM40_4KNR from JSON tree.
Importing module SB_RAM40_4K from JSON tree.
Importing module SB_PLL40_PAD from JSON tree.
Importing module SB_PLL40_CORE from JSON tree.
Importing module SB_PLL40_2_PAD from JSON tree.
Importing module SB_PLL40_2F_PAD from JSON tree.
Importing module SB_PLL40_2F_CORE from JSON tree.
Importing module SB_MAC16 from JSON tree.
Importing module SB_LUT4 from JSON tree.
Importing module SB_LFOSC from JSON tree.
Importing module SB_LED_DRV_CUR from JSON tree.
Importing module SB_LEDDA_IP from JSON tree.
Importing module SB_IO_OD from JSON tree.
Importing module SB_IO_I3C from JSON tree.
Importing module SB_IO from JSON tree.
Importing module SB_I2C from JSON tree.
Importing module SB_HFOSC from JSON tree.
Importing module SB_GB_IO from JSON tree.
Importing module SB_GB from JSON tree.
Importing module SB_FILTER_50NS from JSON tree.
Importing module SB_DFFSS from JSON tree.
Importing module SB_DFFSR from JSON tree.
Importing module SB_DFFS from JSON tree.
Importing module SB_DFFR from JSON tree.
Importing module SB_DFFNSS from JSON tree.
Importing module SB_DFFNSR from JSON tree.
Importing module SB_DFFNS from JSON tree.
Importing module SB_DFFNR from JSON tree.
Importing module SB_DFFNESS from JSON tree.
Importing module SB_DFFNESR from JSON tree.
Importing module SB_DFFNES from JSON tree.
Importing module SB_DFFNER from JSON tree.
Importing module SB_DFFNE from JSON tree.
Importing module SB_DFFN from JSON tree.
Importing module SB_DFFESS from JSON tree.
Importing module SB_DFFESR from JSON tree.
Importing module SB_DFFES from JSON tree.
Importing module SB_DFFER from JSON tree.
Importing module SB_DFFE from JSON tree.
Importing module SB_DFF from JSON tree.
Importing module SB_CARRY from JSON tree.
Importing module ICESTORM_RAM from JSON tree.
Importing module ICESTORM_LC from JSON tree.

2. Executing Verilog backend.
Dumping module `\icebreaker'.

End of script. Logfile hash: 5d1643821b, CPU: user 2.42s system 0.03s, MEM: 69.72 MB peak
Yosys 0.9+3541 (git sha1 04d5692a, clang 6.0.0-1ubuntu2 -fPIC -Os)
Time spent: 87% 2x write_verilog (2 sec), 12% 2x read_json (0 sec)
iverilog -s testbench -o icebreaker_syn_tb.vvp icebreaker_tb.v icebreaker_syn.v spiflash.v `yosys-config --datdir/ice40/cells_sim.v`
icebreaker_tb.v:69: warning: parameter MEM_WORDS not found in testbench.uut.
riscv32-unknown-elf-cpp -P -DICEBREAKER -o icebreaker_sections.lds sections.lds
riscv32-unknown-elf-gcc  -DICEBREAKER -march=rv32ic -Wl,-Bstatic,-T,icebreaker_sections.lds,--strip-debug -ffreestanding -nostdlib -o icebreaker_fw.elf start.s firmware.c
riscv32-unknown-elf-objcopy -O verilog icebreaker_fw.elf icebreaker_fw.hex
vvp -N icebreaker_syn_tb.vvp +firmware=icebreaker_fw.hex
VCD info: dumpfile testbench.vcd opened for output.
0000000
+50000 cycles
+50000 cycles
+50000 cycles
+50000 cycles
+50000 cycles
+50000 cycles
diff --git a/picosoc/Makefile b/picosoc/Makefile
index f600062..77d2b34 100644
--- a/picosoc/Makefile
+++ b/picosoc/Makefile
@@ -10,8 +10,8 @@ hx8ksim: hx8kdemo_tb.vvp hx8kdemo_fw.hex
 hx8ksynsim: hx8kdemo_syn_tb.vvp hx8kdemo_fw.hex
        vvp -N $< +firmware=hx8kdemo_fw.hex

-hx8kdemo.blif: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
-       yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -blif hx8kdemo.blif' $^
+hx8kdemo.json: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
+       yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^

 hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
        iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
@@ -19,11 +19,11 @@ hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../p
 hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v
        iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`

:...skipping...
diff --git a/picosoc/Makefile b/picosoc/Makefile
index f600062..77d2b34 100644
--- a/picosoc/Makefile
+++ b/picosoc/Makefile
@@ -10,8 +10,8 @@ hx8ksim: hx8kdemo_tb.vvp hx8kdemo_fw.hex
 hx8ksynsim: hx8kdemo_syn_tb.vvp hx8kdemo_fw.hex
        vvp -N $< +firmware=hx8kdemo_fw.hex

-hx8kdemo.blif: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
-       yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -blif hx8kdemo.blif' $^
+hx8kdemo.json: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
+       yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^

 hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
        iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
@@ -19,11 +19,11 @@ hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../p
 hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v
        iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`

-hx8kdemo_syn.v: hx8kdemo.blif
-       yosys -p 'read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v'
+hx8kdemo_syn.v: hx8kdemo.json
+       yosys -p 'read_json  hx8kdemo.json; write_verilog hx8kdemo_syn.v'

-hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.blif
-       arachne-pnr -d 8k -o hx8kdemo.asc -p hx8kdemo.pcf hx8kdemo.blif
+hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json
+       nextpnr-ice40 --8k --asc hx8kdemo.asc --pcf hx8kdemo.pcf --json hx8kdemo.json

 hx8kdemo.bin: hx8kdemo.asc
        icetime -d hx8k -c 12 -mtr hx8kdemo.rpt hx8kdemo.asc
@@ -113,7 +113,7 @@ clean:
        rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd
        rm -f hx8kdemo_fw.elf hx8kdemo_fw.hex hx8kdemo_fw.bin cmos.log
        rm -f icebreaker_fw.elf icebreaker_fw.hex icebreaker_fw.bin
-       rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
+       rm -f hx8kdemo.json hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
        rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
        rm -f icebreaker.json icebreaker.log icebreaker.asc icebreaker.rpt icebreaker.bin
        rm -f icebreaker_syn.v icebreaker_syn_tb.vvp icebreaker_tb.vvp
~

make hx8ksynsim with diff applied, this works and gives serial output:

root@660aae5e3d01:/workdir/picosoc# make hx8ksynsim
yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
yosys -p 'read_json  hx8kdemo.json; write_verilog hx8kdemo_syn.v'

 Yosys 0.9+3541 (git sha1 04d5692a, clang 6.0.0-1ubuntu2 -fPIC -Os)

-- Running command `read_json  hx8kdemo.json; write_verilog hx8kdemo_syn.v' --

1. Executing JSON frontend.
Importing module hx8kdemo from JSON tree.
Importing module SB_WARMBOOT from JSON tree.
Importing module SB_SPRAM256KA from JSON tree.
Importing module SB_SPI from JSON tree.
Importing module SB_RGB_DRV from JSON tree.
Importing module SB_RGBA_DRV from JSON tree.
Importing module SB_RAM40_4KNW from JSON tree.
Importing module SB_RAM40_4KNRNW from JSON tree.
Importing module SB_RAM40_4KNR from JSON tree.
Importing module SB_RAM40_4K from JSON tree.
Importing module SB_PLL40_PAD from JSON tree.
Importing module SB_PLL40_CORE from JSON tree.
Importing module SB_PLL40_2_PAD from JSON tree.
Importing module SB_PLL40_2F_PAD from JSON tree.
Importing module SB_PLL40_2F_CORE from JSON tree.
Importing module SB_MAC16 from JSON tree.
Importing module SB_LUT4 from JSON tree.
Importing module SB_LFOSC from JSON tree.
Importing module SB_LED_DRV_CUR from JSON tree.
Importing module SB_LEDDA_IP from JSON tree.
Importing module SB_IO_OD from JSON tree.
Importing module SB_IO_I3C from JSON tree.
Importing module SB_IO from JSON tree.
Importing module SB_I2C from JSON tree.
Importing module SB_HFOSC from JSON tree.
Importing module SB_GB_IO from JSON tree.
Importing module SB_GB from JSON tree.
Importing module SB_FILTER_50NS from JSON tree.
Importing module SB_DFFSS from JSON tree.
Importing module SB_DFFSR from JSON tree.
Importing module SB_DFFS from JSON tree.
Importing module SB_DFFR from JSON tree.
Importing module SB_DFFNSS from JSON tree.
Importing module SB_DFFNSR from JSON tree.
Importing module SB_DFFNS from JSON tree.
Importing module SB_DFFNR from JSON tree.
Importing module SB_DFFNESS from JSON tree.
Importing module SB_DFFNESR from JSON tree.
Importing module SB_DFFNES from JSON tree.
Importing module SB_DFFNER from JSON tree.
Importing module SB_DFFNE from JSON tree.
Importing module SB_DFFN from JSON tree.
Importing module SB_DFFESS from JSON tree.
Importing module SB_DFFESR from JSON tree.
Importing module SB_DFFES from JSON tree.
Importing module SB_DFFER from JSON tree.
Importing module SB_DFFE from JSON tree.
Importing module SB_DFF from JSON tree.
Importing module SB_CARRY from JSON tree.
Importing module ICESTORM_RAM from JSON tree.
Importing module ICESTORM_LC from JSON tree.

2. Executing Verilog backend.
Dumping module `\hx8kdemo'.

End of script. Logfile hash: 93261dbbcd, CPU: user 3.15s system 0.05s, MEM: 86.89 MB peak
Yosys 0.9+3541 (git sha1 04d5692a, clang 6.0.0-1ubuntu2 -fPIC -Os)
Time spent: 87% 2x write_verilog (2 sec), 12% 2x read_json (0 sec)
iverilog -s testbench -o hx8kdemo_syn_tb.vvp hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v `yosys-config --datdir/ice40/cells_sim.v`
riscv32-unknown-elf-gcc  -DHX8KDEMO -march=rv32imc -Wl,-Bstatic,-T,hx8kdemo_sections.lds,--strip-debug -ffreestanding -nostdlib -o hx8kdemo_fw.elf start.s firmware.c
riscv32-unknown-elf-objcopy -O verilog hx8kdemo_fw.elf hx8kdemo_fw.hex
vvp -N hx8kdemo_syn_tb.vvp +firmware=hx8kdemo_fw.hex
VCD info: dumpfile testbench.vcd opened for output.
00000000
00000001
+50000 cycles
00000011
00000111
00001111
00011111
Serial data: 'B'
Serial data: 'o'
Serial data: 'o'
Serial data: 't'
Serial data: 'i'
Serial data: 'n'
+50000 cycles
Serial data: 'g'
Serial data: '.'
Serial data: '.'
Serial data:  13
Serial data:  10
00111111
+50000 cycles
01111111
11111111
Serial data: 'P'
Serial data: 'r'
+50000 cycles
Serial data: 'e'
Serial data: 's'
Serial data: 's'
Serial data: ' '
Serial data: 'E'
Serial data: 'N'
Serial data: 'T'
Serial data: 'E'
Serial data: 'R'
Serial data: ' '
Serial data: 't'
Serial data: 'o'
Serial data: ' '
Serial data: 'c'
Serial data: 'o'
Serial data: 'n'
Serial data: 't'
Serial data: 'i'
Serial data: 'n'
Serial data: 'u'
Serial data: 'e'
Serial data: '.'
Serial data: '.'
Serial data:  13
Serial data:  10
+50000 cycles
void-spark commented 3 years ago

The problem here is that the memory in the synthesized version isn't limited to 256 words, like it is in the non synthesized version. So it's forever initializing memory.