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PicoRV32 - A Size-Optimized RISC-V CPU
ISC License
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Update picorv32.v #186

Open SebastianZa opened 3 years ago

SebastianZa commented 3 years ago

Clocked process for the AXI_BREADY signal.

The BREADY has to go low with BVALID. This was not the case in my simulation. BREADY was one clock cycle longer high than allowed. Here I propose a bugfix, it worked for me and simulation in Modelsim looks good.

Kind regards Sebastian