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PicoRV32 - A Size-Optimized RISC-V CPU
ISC License
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same cycle counts for norm_mul and fast_mul via function simulation. #187

Closed tianyma closed 3 years ago

tianyma commented 3 years ago

Hi, maybe this is a basic question, I am new in IC design. I found that in function simulation, norm_mul and fast_mul have the same cycle counts, which both are 6 cycles, and I cannot figure it out. Can anyone explain it for me?

I use iverilog to compile and gtkwave to view the wave, and I see the signal

pcpi_insn

are both 6 cycles for either normal multiple or fast multiple.

jyukumite commented 3 years ago

Cycle counts definitely longer for mul (pcpi_valid for ~37 clocks) vs fast_mul (~3 clocks) here - on verilator and on the fpga target - perhaps post a snippet of your verilog and I might be able to help.

tianyma commented 3 years ago

Cycle counts definitely longer for mul (pcpi_valid for ~37 clocks) vs fast_mul (~3 clocks) here - on verilator and on the fpga target - perhaps post a snippet of your verilog and I might be able to help.

Thank you, it's my mistake, I set the wrong parameter, and the two tests actually both use fast mul. Now it works.