rdcycle RISC-V instruction giving too high number of clock cycles

[SyedFahimuddinAlavi]

I am using rdcycle instruction to calculate number of clock cycles consumed for operation but I see some high number of clock cycles on PicoRV32 with Verilator. So I tried basic code of a++

  register int a=0;

  Begin_Time = time ();
  a++;
  End_Time = time ();
  print_str("a++ ......

output:

a++ cycles:56, Begin cycles:18495, End cycles:18551

But the problem is that the 56 clock cycles are too way big to do a++. Yes function call is taking some clock cycles but instead of a++ even if it is an local array like a[i]=1 than it is consuming 82 clock cycles(26 clock cycles more than a++). I am understanding something wrong or it is against RISC-V specifications?

Note : rdcycle is used in time function

static long time(void)
{
    long cycles;
    __asm__ volatile ("rdcycle %0" : "=r"(cycles));
    // printf("[time() -> %d]", cycles);
    return cycles;
}

[johnwinans]

Did you look at the assembly output from the compiler? Did the compiler not inline your time function?

[SyedFahimuddinAlavi]

Thanks for reply. I forgot to check assembly output but problem was that actually function call was consuming a lot of cycles. I modified a lit bit and cycles consumed dropped to 7 cycles(difference of begin and end) so a++ is actually just taking 1 clock cycle as expected and remaining 6 clock cycles are consumed for bench-marking like rdcycle instruction itself, PC increment etc. if I understand correctly

        __asm__ volatile ("rdcycle %0" : "=r"(Begin_Time));
        a=a+1;
       __asm__ volatile ("rdcycle %0" : "=r"(End_Time));