Fmax and latency on PicoRV32

YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

ISC License

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Fmax and latency on PicoRV32 #265

Open SyedFahimuddinAlavi opened 4 months ago

SyedFahimuddinAlavi commented 4 months ago

I have modified the Pico RISC-V core with crypto algorithms and want to get updated Fmax. Is there any way to calculate the latency introduced without running on FPGA using any example or test in simulation?

KrystalDelusion commented 4 months ago

It may be out of date, but the fmax tables in the readme were apparently generated with the makefile in scripts/vivado/Makefile?