Incorrect vector length seen in VCD

[Harshitha172000]

I asserted some properties to check the following code.

for (i = 0; i < NUMWAYS; i = i + 1) begin         
       if (access[i]) begin         
           for (j = 0; j < NUMWAYS; j = j + 1) begin              
                 if (i != j) begin                  
                   expand[i][j] = 1'b0;              
                 end       
          end         
           for (j = 0; j < NUMWAYS; j = j + 1) begin          
                 if (i != j) begin                
                    expand[j][i] = 1'b1;               
                end           
         end        
 end      
end 

I ended up with the following error where the last row of the expand vector has only 3 bits instead of 4.

Later, I asserted properties to check whether all vectors of the expand array are of the same length, then the test passed.

VCD showing up incorrect vector length for the above code snippet.

[jix]

I can't reproduce this nor see how this could happen with the current version of sby and yosys. There have been changes in the meantime, so it might have been fixed by one of those. If this issue still persists with a current sby and yosys version, please provide a complete runnable example, not just a snippet.