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SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
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Unexpected assertion behaviour #128

Closed saw235 closed 3 years ago

saw235 commented 3 years ago

Not sure if this is a bug, but I am getting failed assertion on the assert statement below, even though the counterexample waveform shows that data_wr_strobe is stable across two cycles. Which should make the assertion vacuously True, if I understand it correctly. image image

piegamesde commented 3 years ago

To help finding out more about the issue, please try to minimize the code example: strip away piece after piece while checking that the assertion fails although it shouldn't until you cannot remove any more without making it work again.

saw235 commented 3 years ago

Hi even after I stripped down to its bare minimum, it is unclear what is happening. The following assertion below fails even though in the waveform it looks stable for 2 cycles to me.

My only guess is that the $stable() does not work like I understand it to be, or that the initial value starts off as 'X' and changes to 0 which makes the assertion fails. In the second case, I have no clue how I can get the tool to ignore time 0.

image image

EngRaff92 commented 3 years ago

Your clk starts as one meaning there is an active edge there, make an initial where you set the clk to 0, then in clk gen do always # clk = ~clk. To ignore time zero let the assert not be triggered by simply avoid using an evaluation point at that time. Properties has disable iff to let it be settled under reset

saw235 commented 3 years ago

@EngRaff92 Thanks. I figured out what's wrong and managed to come up with a solution to ignore the first cycles by referencing the ibex repository.