Closed Seek64 closed 2 years ago
No, unfortunately hierarchical access is only possible using the verific frontend (available in the commercial Tabby CAD Suite only). There is an effort to implement it for read_verilog
by an external contributor but it seems currently stalled: https://github.com/YosysHQ/yosys/pull/2752
Thank you for the response. I will then resort to the workaround for the time being and also have a look at the PR.
Hello everyone,
I was playing around with the unbounded prover example:
My question is if there is a way to access the submodule signals from the testbench itself? Essentially, what I would like to do is something like:
If I try it like this, what I get is the following warning
and the assertion is ignored during the proof.
The two workarounds I tried were
Both of them worked. For my use case, however, I would like to compare the signals of the different submodules. Therefore, only the second option would be viable. However, creating a separate output for each signal I want to compare seems very cumbersome, so I would like to know if hierarchical access is also possible somehow?