Closed albydnc closed 1 year ago
Reviewing your image alone, this looks like the correct tool behavior. The issue associated with a toggle on the last step, when the clock doesn't rise, is the correct behavior: since the clock hasn't risen (yet), or more specifically since the global clock hasn't risen yet, there's no ability to evaluate $rose. You have to wait one more time step.
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Dan
Hello,
I'm trying to verify a multiclock design. I took example from the @ZipCPU async FIFO to setup the signals. here is the part of the formal definition that is not working as expected:
since
ready_ST_sink_data_processing_out
is not kept stable, assertions$stable
onready_ST_source_tfc_processing
andready_ST_source_data_processing
are failing.I added the VCD and the waveform issue as jpg.
ut));
vcd_out.zip