Closed AdamKeith1 closed 1 month ago
Try creating a new wire as e.g. (* hierconn *) wire \MODB.and_i ;
and make sure you run flatten
on your design. Then use this wire in your assertion.
Also, `default_nettype none
instructs Verilog frontends to not automatically create wires for unknown identifiers.
Ok a few questions.
(* hierconn *)
? I've never seen this before. (found it on Yosys repo)Sorry if this is a lot.
- what is
(* hierconn *)
? I've never seen this before.
A Yosys-specific extension which allows you to address a wire from an inner module. It is recognized by the flatten
pass and otherwise the wire is inert.
- how to incorporate flatten, is it a command line option or something that needs configured in .sby file
Use prep -top top -flatten
instead of prep -top top
.
- I have default nettype set to none and then set back to wire should it just be none?
If you set it to wire
you request any unknown identifier to be created as a new wire. This is a bad idea generally.
4. I'm looking to make sure that the actual values in the ports for mod_a and mod_b are equal for the whole 'sim', so I'm nopt necessarily looking to make a new wire unless necessary.
No new wire is created, the wire
declaration is just a phantom construct Yosys uses internally to fill in standard SystemVerilog functionality that it is missing.
Thank you so much for the quick response. This is a super small design to use as a proof of concept before I test a large design. Is there a way to include an entire folder of a lot of design files in the [files] section or do I have to reference the path for them all individually, there's also pycode plots and I was wondering if there's a way to like use an external yaml file with pycode in the sby file to add all my design files.
You could use pycode blocks, yes. I don't think there's any functionality that traverses a directory out of the box.
So I have vhdl designs that references packages, say for example USE work.axi_pkg.ALL
. So I include that package in my [files] section but because it's referenced in the work library it doesn't get recognized by the actual design (not my duts are vhd and my tb is sv). How can I get those files into a place my dut will recognize them without modifying the source code?
I honestly have no idea, I don't use GHDL (or SystemVerilog for that reason).
I am trying to verify connectivity between two modules. It seems that when I make the assertion, it created an identical net to the signal I want to reference and thinks it's poorly written identifier. I'll post my code and some other snippets below. The modules are simple just to use as a proof of concept for checking connection between two modules using sby. It seems to just think I didn't declare the wire and then makes a new instance even though the name in the hierarchy is the same as the signal I want to reference.
connect.sby...
a.sv...
b.sv...
tb.sv
console output...
trace.vcd...