EDIF backend not recognising my hadder edif module

[jameswalmsley]

Hi Clifford,

module hadder(a, b, s, c);

   input a, b;
   output s, c;

   assign s = a ^ b;
   assign c = a & b;

endmodule // hadder

module adder(ci, a, b, s, co);

   input ci, a, b;
   output s, co;

   wire u0_sum_out;
   wire u0_carry_out;
   wire u1_carry_out;

   hadder u0 (a, b, u0_sum_out, u0_carry_out);
   hadder u1 (ci, u0_sum_out, s, u1_carry_out);

   assign co = u0_carry_out | u1_carry_out;                   

endmodule // adder

/**
 * Using our half adder implementation and full-adder, we can chain them together into a
 * 4-bit ripple carry adder.
 * 
 **/
module top(sw_0, sw_1, sw_2, sw_3, sw_4, sw_5, sw_6, sw_7, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);

   input sw_0, sw_1, sw_2, sw_3, sw_4, sw_5, sw_6, sw_7;
   output led_7, led_6, led_5, led_4;
   output led_3, led_2, led_1, led_0;

   wire   b0_sum, b0_carry;
   wire   b1_sum, b1_carry;
   wire   b2_sum, b2_carry;
   wire   b3_sum, b3_carry;

   hadder b0 (sw_0, sw_4, b0_sum, b0_carry);    // Bit 0 is just as half adder, as we have no carry in :)
   adder  b1 (b0_carry, sw_1, sw_5, b1_sum, b1_carry);
   adder  b2 (b1_carry, sw_2, sw_6, b2_sum, b2_carry);
   adder  b3 (b2_carry, sw_3, sw_7, b3_sum, b3_carry);

   assign {led_7, led_6, led_5} = 0;
   assign {led_4, led_3, led_2, led_1, led_0} = {b3_carry, b3_sum, b2_sum, b1_sum, b0_sum};   

endmodule // top

Synthesises perfectly in yosys, but edif2ngd gives me an error:

+ /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/edif2ngd -a synth.edif synth.ngo
Release 14.7 - edif2ngd P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 14.7 edif2ngd P.20131013 (lin64)
INFO:NgdBuild - Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild:1406 - Converting edif 'integer' property 'INIT' with value '14'
   on object '$abc$73$auto$blifparse.cc:119:abc_parse_blif$74.lut2.fpga_lut' to
   'hexadecimal' property.
ERROR:NgdBuild:175 - On or above line 75 in file "synth.edif":  Reference to an
   unknown cell "hadder".  This likely means that the EDIF netlist was
   improperly written.  Please contact the vendor of the program that produced
   this EDIF file.

I feel like I should try to fix this myself, but have no idea where to start.

[jameswalmsley]

Ok on closer inspection it looks like the hadder module is referenced on line 75 (cellref hadder), but the actual cell is defined below it.

Looks like the deepest parts of the hierarchy need to be declared at the top.

[jameswalmsley]

Confirmed, if I edit the edif file manually to put the hadder cell above the adder cell, then Xilinx accepts it. I took a quick look at how the edif backend works, but still trying to work it out. :)

[jameswalmsley]

Awesome, the ripple carry adder works on zedboard :)

[cliffordwolf]

ack. I'll add topological sorting to the edif backend.

[cliffordwolf]

I just pushed commit cd0fe7d which contains topological sorting in edif backed.

[jameswalmsley]

Cheers :)